От: D&R SoC NewsAlert [SoC-NewsAlert@design-reuse.com]
Отправлено: 4 января 2005 г. 14:20
Кому: Michael Dolinsky
Тема: D&R SoC News Alert - January 4, 2005
DR SoC News Alert
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January 4, 2005    


Michael,
Welcome to issue of January 4, 2005 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

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    ST NAND128-A Flash Memory VITAL Model from HDL Design House
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  • Understanding and Extending SystemC UserThread Package to IA64 Platform
    Array Processors Enable Flexibility in FFT Designs
    An introduction to Product Lifecycle Management (PLM) for EDA
    Japanese companies look to integrate, not outsource
    How to select verification IP
    IP/SOC PRODUCTS
    Wipro's MBOA MAC IP scheduled for release by early Q2, 2005
    Tahoe RF Semiconductor Validated as 'Ready for IBM Technology' for Additional IBM Technologies
    FINANCIAL RESULTS
    ARM Announces Results of Stock Elections in the Acquisition of Artisan Components, Inc.
    LEGAL
    Hitachi Files Patent Infringement Complaint against GS Magicstor Companies
    PEOPLE
    MoSys Co-Founder and CEO Fu-Chieh Hsu Resigns
    EMBEDDED SYSTEMS
    LSI Logic Enables DivX(R) Encoding for DVD Recorders With DoMiNo(R) 8603 Single-Chip Processor
    FOUNDRIES
    Tower Semiconductor Announces Closing of Sale of Its Shares in Saifun Semiconductor
    Chartered secures financing for Fab 7
    austriamicrosystems HIT-Kit offers comprehensive cell libraries to foundry customers free of charge
    austriamicrosystems MPW Shuttle prototyping service hits 10,000 customer orders
    TSMC Announces Nexsys 90 Nanometer Volume Production
    EDA
    CoWare Forges Relationships with Premier Universities in India to Accelerate Research and Development in ESL Tools and Methodologies
    Aldec Releases Integrated SystemC Debugging Environment with Assertion-Based Verification

    SPONSORED BY: TEMENTO SYSTEMS

    Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

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